1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which performs an acceleration test (a burn-in test) for detecting an internal short-circuited path.
2. Description of the Background Art
In a semiconductor memory device such as a dynamic random access memory (DRAM), a short-circuited path sometimes generates between a bit line and a node other than the bit line in fabrication. If a leak current which is generated on the short-circuited path is minute, it is difficult to detect the short-circuited path by a normal operation test. In the present specification, such a short-circuited path which causes only a minute leak current at a normal operating voltage and which is thereby difficult to detect will be sometimes referred to as “minute leak path”.
If a semiconductor memory device is provided as a finished product without detecting a minute leak current, problems of a low in operation margin and an increase in power consumption arise as a result of the generation of a stationary minute leak current. In order to ensure rejecting semiconductor memory devices which have such minute leak paths, therefore, a burn-in test for detecting the minute leak paths by applying a voltage stress higher than that at the time of the normal operation is normally performed. Various configurations for applying a predetermined high voltage to a bit line in the burn-in test have been proposed so far.
In order to prevent thin film transistors which constitute a sense amplifier circuit from being destroyed by applying a high voltage to a bit line at the time of the burn-in test, a configuration that the bit line is separated from the sense amplifier circuit at the time of the burn-in test is disclosed for example in Japanese Patent Laying-Open No. 2001-68634.
Further, a configuration that predetermined voltages are applied to each of bit lines in order to perform batch data writing at the time of a test mode and a configuration that different levels of voltages (high and low voltages) are applied to each of bit lines in odd-numbered columns and each of bit lines in even-numbered columns, although they are not directly relevant to a burn-in test, are disclosed for example in Japanese Patent Laying-Open No. 10-269775.
There are a plurality of types of minute leak paths for bit lines, so that minute leak currents may generate between a bit line and a node other than the bit line (e.g., a word line) and between the bit lines. With a folded bit line configuration, a minute leak current may possibly generate between complementary bit lines which constitute the same bit line pair.
For example, a minute leak path between a bit line and a node other than the bit line can be detected by applying the same high voltage to each of the bit lines in a burn-in test. However, in order to detect the minute leak path which generates between the bit lines, it is necessary to set different voltages to adjacent bit lines. With the folded bit line configuration, in particular, it is necessary to apply a voltage stress a portion between complementary bit lines which constitute the same bit line pair or between the bit lines equal or opposite in phase.
With each of the configurations disclosed in the patent publications, it is impossible to detect all the various types of minute leak paths which generate to the portions between the bit lines only by the burn-in test in a state where the sense amplifier circuit is separated from the bit lines. In other words, it is necessary to perform a burn-in test for applying a high voltage to the bit line by writing data through the sense amplifier circuit. Such a burn-in test, however, may possibly destroy thin film transistors in the sense amplifier circuit, so that it is difficult to perform the burn-in test.